The present invention relates to conductive/inductive transmission lines and, in particular, to discrete thin and thick film components having predetermined signal delay characteristics determined from tailored inductive/capacitive impedance characteristics and providing unitary nanosecond delays which components may be used to populate conventional printed circuit (PC) boards.
With the ever constant pressure to improve the speed performance of a wide variety of digital and analog switching and signal processing technologies, a need exists for high reliability, nanosecond delay lines to accommodate certain precision timing requirements of such circuit designs. Although a wide variety of techniques and technologies have been used to develop precise time interval defining circuits, they have been principally directed to relatively long duration delays in the millisecond to microsecond range, have required a number of circuit components to implement and/or are relatively costly. In contrast and in many circumstances a high precision, small size discrete component, nanosecond delay line is preferred.
One transmission line type delay element of which Applicant is aware and which Applicant currently produces comprises a discrete packaged assembly having a serpentine patterned conductive layer plated/etched onto one side of a relatively thick, dielectric substrate and on an opposing side of which is formed a ground plane. The substrate is used not only as a mechanical support but also for its dielectric properties to separate the ground plane from the serpentine conductor. Although requiring relatively few layers, this construction is limited in the magnitude of delay which is achievable which typically does not exceed 1.7 nanoseconds. Unit delays for a similar single conductor layer of predetermined length and package size on the order of 5 to 10 nanoseconds are preferred. An improved delay range particularly increases the range of components which may be constructed relative to an end user's circuit designs.
The particular limitation which Applicant believes has heretofore limited its ability to achieve an increased range of delay values has resulted from an inability to obtain suitable dielectric substrates thinner than 0.4 millimeters. In particular, the relatively thick dielectric has constrained the conductor widths and spacings to the point where the device's inductive and capacitive characteristics provide for a combined device impedance which is insufficient to achieve the preferred delays. That is, with a thinner dielectric the device's capacitive characteristics vis-a-vis the ground plane and inductive characteristics vis-a-vis the windings of the serpentine conductor may be tailored to increase the device's measured overall impedance (Z.sub.0) and resultant time delay.
One other construction of which Applicant is aware is produced by Valor Electronics, but which is constructed more in the fashion of a coiled so-called "lumped constant" LC configuration. Such devices however do not lend themselves to the range of delays which Applicant now seeks, to obtain, and rather find use where delays greater than 10 nanoseconds are required. They also tend to exhibit poor temperature coefficients and are more commonly constructed from discrete inductor and capacitive components, rather than as film devices.